"flags" in x86 Linux's /proc/cpuinfo

Ever wonder what these "flags" in x86 Linux's /proc/cpuinfo mean ? Here is the answer (from Linux kernel source file arch/x86/include/asm/cpufeature.h):

3dnow AMD 3DNow!
3dnowext AMD 3DNow! extensions
3dnowprefetch 3DNow prefetch instructions
abm AMD Advanced Bit Manipulation instruction, i.e. LZCNT (Count leading zero bits)
ace VIA Advanced Cryptography Engine, i.e. XCRYPTxxx instructions
ace_en ACE enabled
ace2 VIA Advanced Cryptography Engine v2
ace2_en ACE v2 enabled
acpi ACPI (Advanced Configuration and Power Interface) via MSR (Model-Specific Register)
aes AES (Advanced Encryption Standard) instructions
amd_dcm AMD multi-node processor (DCM=Direct Connect Module)
aperfmperf Actual Performance Clock Counter (APERF) and Maximum Qualified Performance Clock Counter (MPERF) in MSRs
apic On-chip APIC (Advanced Programmable Interrupt Controller)
arat Always running APIC timer
arch_perfmon Intel Architectural PerfMon
AVX (Advanced Vector eXtensions)
Intel 1st/2nd group advanced bit manipulation extensions. The first group includes instructions such as ANDN, BEXTR, BLSI, BLSMK, BLSR, TZCNT, and the second group, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX.
bts Branch Trace Store
centaur_mcr Centaur MCRs (= MTRRs, Memory Type Range Registers)
cid L1 Context ID: the L1 data cache can be set to adaptive or shared mode by the BIOS
clflush CLFLUSH (Cache line flush) instruction
cmov CMOV (conditional move) instructions (plus FCMOVcc, FCOMI with FPU)
cmp_legacy If yes HyperThreading not valid
constant_tsc Time Stamp Counter ticks at a constant rate
cpb AMD Core Performance Boost
cr8_legacy CR8 (Control Register #8, a.k.a. TPR: Task Priority Register) in 32-bit mode
cx16 CMPXCHG16B instruction
cx8 CMPXCHG8 instruction
cxmmx Cyrix MMX extensions
cyrix_arr Cyrix ARRs (= MTRRs)
dca Direct Cache Access (the ability to prefetch data from MMIO)
de Debugging Extensions
decodeassists AMD Decode Assists support
ds_cpl CPL-qualified debug store (CPL=Current Privilege Level)
dtes64 64-bit Debug Store
dts Debug Store
dts Digital Thermal Sensor
epb Intel Energy Performance Bias MSR
ept Intel Extended Page Table
erms Intel enhanced REP MOVSB/STOSB instructions
est Intel Enhanced SpeedStep
extapic Extended APIC space
extd_apicid Has extended APICID (8 bits)
f16c 16-bit floating-point conversion instructions
flexpriority Intel FlexPriority
flushbyasid AMD flush-by-ASID (Address Space ID) support
fma Fused multiply-add instructions
fma4 AMD 4-operand fused multiply-add instructions
fpu On-chip Floating-Point Unit
fsgsbase Intel FS/GS Base registers access instructions, part of AVX
fxsr FXSAVE/FXRSTOR instructions
fxsr_opt AMD (fast) FXSAVE/FXRSTOR optimizations
hle Intel Haswell hardware lock elision (transactional memory support)
ht Intel Hyper-Threading
hypervisor Running on a hypervisor
ia64 IA-64/Itanium processor
ibs AMD Instruction Based Sampling
ida Intel Dynamic Acceleration
invpcid Intel invalidate processor context ID
k6_mtrr AMD K6 nonstandard MTRRs
lahf_lm LAHF/SAHF (Load/Store Flags into AH Register) instruction in Long Mode
lbrv AMD LBR (Last Branch Record) Virtualization support
lm Long Mode (x86-64)
longrun Transmeta LongRun power control
lrti Transmeta LongRun table interface
lwp AMD Light Weight Profiling
mca Machine Check Architecture
mce Machine Check Exception
misalignsse AMD's misaligned accesses for SSE instructions
mmx MMX (MultiMedia eXtensions)
mmxext AMD MMX extensions
monitor MONITOR/MWAIT instructions
movbe MOVBE (MOV with Bi-Endian support, i.e. swapping the high & low bits of a long value during a MOV) instruction (currently only available on Intel Atom processors)
mp AMD Athlon MP (MultiProcessor) Capable
msr Model-Specific Registers
mtrr Memory Type Range Registers
nodeid_msr AMD NodeId MSR
nonstop_tsc Time Stamp Counter does not stop in C states
nopl The NOPL (0F 1F) instructions; 21 available, was AMD_C1E
npt AMD Nested Page Table
nrip_save AMD SVM Next RIP Save: Save next sequential instruction pointer on Virtual Machine exit
nx No eXecute
osvw AMD OS Visible Workaround
pae Physical Address Extensions
pat Page Attribute Table
pausefilter AMD filtered pause intercept
pbe Pending Break Enable
pclmulqdq PCLMULQDQ instruction
pdcm Performance & Debug Capability MSR
pdpe1gb AMD 1-GB large page support (PDPE=Page-directory-pointer entry)
pebs Intel Precise-Event Based Sampling
perfctr_core AMD Bulldozer (Family 15h) core performance counters
pfthreshold AMD pause filter threshold
pge Page Global Enable: the global bit in the Page Directory Entries (PDE) & Page Table Entries (PTE) is supported
phe VIA PadLock Hash Engine, i.e. XSHA1/XSHA256 instructions
phe_en PHE enabled
pln Intel Power Limit Notification
pmm VIA PadLock Montgomery Multiplier, i.e. MONTMUL instruction
pmm_en PMM enabled
pn Processor serial number
pni SSE-3 (Prescott New Instructions)
popcnt AMD POPCNT instruction
pse Page Size Extensions
pse36 36-bit PSEs
pts Intel Package Thermal Status
rdrnd Intel RDRAND instruction, part of AVX
rdtscp AMD RDTSCP instruction
recovery Transmeta CPU in recovery mode
rep_good REP instruction works well
rng VIA Random Number Generator, i.e. XSTORE instruction
rng_en RNG enabled
rtm Intel Haswell restricted transactional memory
sep Intel SYSENTER/SYSEXIT instructions (for fast system calls)
skinit AMD SKINIT/STGI (Secure kernel init & jump with attestation/Set global interrupt flag) instructions
smep Intel Supervisory Mode Execution Protection
smx Intel Safer Mode eXtensions, part of the Intel Trusted eXecution Technology (TXT)
ss Intel CPU self snoop
sse SSE (Streaming SIMD Extensions)
sse2 SSE-2
sse4_1 SSE-4.1
sse4_2 SSE-4.2
sse4a SSE-4A
ssse3 Supplemental SSE-3
svm AMD Secure Virtual Machine (i.e. AMD-V, V for Virtualization)
svm_lock AMD SVM lock
syscall AMD SYSCALL/SYSRET instructions (for fast system calls)
tbm AMD Trailing Bit Manipulation instruction
tm Thermal Monitor
tm2 Thermal Monitor 2
topoext AMD processor topology extensions
tpr_shadow Intel TPR (Task Priority Register) Shadow
tsc RDTSC (Read Time Stamp Counter) instruction
tsc_reliable Time Stamp Counter is known to be reliable
tsc_scale AMD MST-based Time Stamp Counter scaling/rate control
unfair_spinlock Use unfair spinlock when running on hypervisor
up SMP kernel running on up
vmcb_clean AMD VMCB (Virtual Machine Control Block) clean bits support
vme Virtual Mode Extensions
vmx Intel Virtual Machine eXtensions
vnmi Intel Virtual NMI (Non-Maskable Interrupts)
vpid Intel Virtual Processor ID
wdt AMD Watchdog Timer
x2apic x2APIC/processor topology
xop AMD eXtended OPeration instructions (was: SSE5)
xsaveopt Optimized XSAVE
xtopology Extended topology enumeration CPUID leaf 0xb, as in arch/x86/kernel/cpu/topology.c
xtpr Intel xTPR update control: Can disable sending Task Priority messages

Also, check this link.

Ever wonder what these "power management" in x86 Linux's /proc/cpuinfo mean ? Here is the answer (from Linux kernel source file arch/x86/kernel/cpu/powerflags.c). They are AMD's advanced power management:

100mhzsteps 100 MHz multiplier control
fid Frequency ID control
hwpstate Hardware P-state control (P=Performance)
stc Software thermal control
tm Hardware thermal control
ts Temperature sensor
ttp Thermal trip
vid Voltage ID control